1. Field of the Invention
The present invention relates to the process of estimating capacitance in an integrated circuit. More specifically, the present invention relates to the process of estimating parasitic capacitance in an integrated circuit by using a set of Green's functions.
2. Related Art
Throughout recent history, the relentless miniaturization of integrated circuits has been a key driving force behind technological innovation. Today, integrated circuits are being built at deep sub-micron (DSM) dimensions. At these dimensions, accurate estimation of parasitic capacitances has become absolutely critical for performing any subsequent timing or signal integrity analyses.
Parasitic capacitances, which could previously be extracted using simplified methods, are now more difficult to compute because of the increased effect of fringe capacitances at small dimensions. Moreover, since miniaturization is expected to continue, accurate estimation of parasitic capacitance is expected to become even more critical in the future.
Hence, there is a pressing need to use sophisticated three-dimensional (3-D) methods for extracting capacitances for integrated circuits. However, it is well known that 3-D methods require large processing times and many of these methods do not scale well. Hence, 3-D methods have typically been used for estimating capacitances for small to medium sized integrated circuits.
3-D methods can broadly be classified into Finite Element Method (FEMs), Fast Multipole Methods (FMMs), Boundary Element Methods (BEMs) and statistical methods. All of these methods compute capacitance by solving fundamental electrostatic equations, albeit using different numerical techniques. Moreover, in all of these methods, capacitances are computed indirectly by evaluating a charge integral.
In particular, FEM-based methods evaluate the charge integral by discretizing the entire volume of the integrated circuit and then solving the resultant linear system. BEM-based methods only discretize the conductor boundaries and dielectric interfaces. Even though this approach reduces the size of the resultant linear systems, they still result in large linear systems. Both FEMs and BEMs are computationally infeasible to solve for large integrated circuits. Hence, these methods are useful only for computing capacitances for small to medium sized integrated circuits.
FMM-based methods use efficient heuristics to reduce the size of the linear systems generated by the BEM-based methods, thereby facilitating their applicability to larger integrated circuits. Still these methods are infeasible to solve large integrated circuits.
In contrast, statistical methods can be used for estimating capacitance for large integrated circuits. Instead of discretizing volumes or boundaries, statistical methods estimate the capacitance by statistically sampling the integrand in the charge integral. Since statistical methods do not discretize volumes or boundaries, they can be used to estimate the capacitance for large integrated circuits without significantly increasing the processing time.
Unfortunately, present statistical methods for estimating capacitances suffer from two main drawbacks. First, present statistical methods tend to be inefficient if the integrated circuit contains multiple layers of dielectrics. Nowadays, it is common to have three or more layers of dielectrics between conductors in an integrated circuit. Hence, it is not practical to use existing statistical methods to estimate capacitance. Second, existing statistical methods have slower convergence properties and tend to report capacitance estimates with larger variance in given computation time. To get capacitance estimates with smaller variance requires large amount of computational time. Since the subsequent timing or signal integrity analyses is highly sensitive to the accuracy of the estimated capacitance, having a large variance in the estimated capacitance can have a detrimental effect in these subsequent analyses.
Hence what is needed is a method and apparatus for accurately and efficiently estimating the parasitic capacitance in a large integrated circuit with multiple dielectrics.